Implement 2-Bit Saturating Counter Branch Predictor

Saturating Counter States

A 2-bit saturating branch predictor keeps four states per branch: strongly not-taken (00), weakly not-taken (01), weakly taken (10), strongly taken (11). Correct predictions nudge one step toward taken/not-taken; mispredictions snap or reverse.

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Why Two Bits Beat One

A single bit thrashes on loops: the final backward branch looks not-taken once, causing a mispredict every iteration. Two bits remember "usually taken" after warm-up.

For example, a for (i=0; i<1000; i++) back-edge transitions from SNT to ST over the first handful of iterations, then stays correct.

For this exercise, you will simulate a table of 2-bit counters keyed by PC and report accuracy on traces. This task asks you to beat a static always-taken baseline on mixed branch workloads.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.