ARM Registers: x0-x30, sp, lr, pc

Thirty-One GPRs Change Calling Conventions

AArch64 exposes x0-x30 plus sp and xzr. More registers than x86 means Clang spills less often, part of why Apple Silicon feels fast at modest clocks. w0 is the low 32 bits of x0; writing w0 zero-extends into x64.

Roles You Will Use

• x0-x7: arguments per AAPCS64; x0 returns scalars
• x9-x15: temporaries, caller-saved
• x19-x28: callee-saved, preserve if you touch them
• x29: frame pointer; x30 (lr): return link
• v0-v31: NEON/SIMD, aliased as q, d, s lanes

asmCopy
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For this exercise, you will move immediates through several registers and print results with sys_write. This task asks you to mix x and w forms deliberately, because ABI docs and crash logs report both names for the same physical register.

Keep the relevant man page, ABI doc, or Rust reference chapter open while you work. When your output disagrees with the reference implementation on the same machine, the mismatch is usually an alignment rule, an off-by-one terminator, or a register slot you misread in GDB. Skim the official documentation for the tool or ABI named in the exercise; the prose changes, but register roles, syscall numbers, and ownership rules stay stable across releases. Treat each failure as a contract test: the CPU, kernel, and borrow checker enforce rules whether or not the tutorial mentioned them explicitly.