Upgrade SSE2 Code to AVX2 for 256-bit Vectors

256-bit AVX2 Vectors

AVX2 widens integer and floating SIMD to 256 bits (__m256i). One VADDPS fuses eight 32-bit floats, doubling theoretical throughput versus SSE on the same core (when ports support AVX).

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Frequency Scaling Caveat

Some Intel CPUs downclock when AVX-heavy code runs (AVX-512 more so). Measure end-to-end time, not just instruction count.

• Port 32-byte aligned buffers with _mm256_load_ps
• Compile with -mavx2 -mfma as needed
• Peel epilogues when length not divisible by 8

For this exercise, you will port your SSE2 kernel to AVX2 and compare GB/s. This task asks you to handle remainder elements scalarly while keeping the hot loop on __m256 operations.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.