Measure L1/L2/L3/RAM Latency with Pointer Chasing

Pointer Chasing

Cache latency benchmarks avoid compiler optimizations by chasing pointers through a large buffer. Each load depends on the previous address, serializing memory access and exposing true RAM or cache miss cost.

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Typical Latencies (order of magnitude)

• L1: ~4 cycles
• L2: ~12 cycles
• L3: ~40 cycles
• DRAM: ~200+ cycles

Sweep array size from 4 KiB (fits L1) to 64 MiB (exceeds last-level cache) and plot nanoseconds per access.

For this exercise, you will implement pointer chasing and print latency versus working set size. This task asks you to measure the cliff when data falls out of each cache level, grounding every optimization task that follows in real hardware numbers.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.