IPC, cache-miss rate, and branch-misprediction rate are the first three numbers Intel's own optimization manuals tell engineers to check, because they explain the gap between a CPU's theoretical throughput and what it actually delivers on Skylake- and Zen-class cores. Google's data-center teams read these same perf_event counters fleet-wide via 'perf stat' to decide whether a service is memory-bound before anyone touches a line of code.