Program the 8259 PIC for Interrupt Management

8259 PIC programming

The dual 8259 PICs cascade IRQ 8-15 through IRQ2. Initialization (ICW1-4) sets vector offsets, edge/level mode, and master/slave wiring. For example, remapping IRQ0-7 to vectors 0x20-0x27 avoids conflicts with CPU exceptions at vectors 0-31.

Remap sequence

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• Mask registers 0x21/0xA1: Bit set disables IRQ line
• EOI: Send 0x20 to master; slave IRQ also needs 0x20 to port 0xA0
• Read ISR/IRR: Poll in-service vs pending during debugging
• Modern ACPI systems may use IOAPIC instead, but PIC bring-up still teaches the flow

Spurious IRQ7

IRQ7 can fire spuriously when noise hits the cascade line; read ISR to see if a real interrupt is in service. Slave PIC sits on IRQ2 of the master; forgetting cascade ICW2 leaves keyboard and timer dead. Unmask only the IRQ lines you have ISRs for; leaving all unmasked without handlers causes nested fault storms. Document the vector base you choose so IDT indices match remap values.

Why for this exercise

You will remap the PIC and unmask only the IRQ lines your handler needs. This exercise requires writing the ICW sequence and matching IDT vector bases to the remap values.