Implement Direct-Mapped Cache Simulator

Cache Indexing

A direct-mapped cache splits physical addresses into tag, index, and offset. Each index maps to exactly one cache line; conflicts evict even if other lines sit idle.

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Hit and Miss

On access:

1. Compare stored tag at index with computed tag
2. Check valid bit
3. Hit: return data; miss: fetch line from memory, replace entry

For example, with 64-byte lines and 256 lines, index is 8 bits and two addresses that agree on those bits contend for the same slot.

For this exercise, you will simulate loads and stores, counting hits and misses. This task asks you to implement tag compare and line fill, the same mechanics perf indirectly observes when LLC miss rate spikes.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.