Demonstrate False Sharing and Cache Coherency Overhead

Cache Lines and Coherence

CPUs move data in cache lines (typically 64 bytes). Two independent variables sharing a line sit on the same coherence unit. When one core writes byte 0 and another writes byte 63, both cores invalidate each other's copy even though logical data differs. That is false sharing.

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Measuring the Pain

Pad structures to one hot field per line:

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Run two threads updating adjacent ints vs padded ints and compare perf c2c or cycle counts.

For this exercise, you will demonstrate slowdown from unaligned hot fields. This task asks you to fix layout with padding and measure the speedup, a routine optimization in Java @Contended, Linux per-CPU counters, and game engine job structs.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.