Master the fundamental concepts of cpu design through this focused micro-challenge.
Forwarding (bypassing) routes a computed result from EX, MEM, or WB directly to the EX stage input muxes, avoiding a register-file round trip. This kills most data hazards without stalling.
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For example, after ADD R1, R2, R3 immediately followed by SUB R4, R1, R5, the SUB in ID needs R1 while ADD is still in EX. Forwarding picks the ALU output from EX/MEM instead of reading the old register value.
For this exercise, you will implement muxes that select the youngest matching producer. This task asks you to compare IPC with and without forwarding on synthetic hazard-heavy code.
Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.
For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.
Implement forwarding to eliminate pipeline stalls.
Requirements:
Three hints are available for this task, revealed one at a time inside the code workspace so you can struggle productively before seeing them.
All starter code and reference implementations are available for your local setup.
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