The GPU Memory Hierarchy: Registers to VRAM

Write a C program that models GPU memory latency and bandwidth at each hierarchy level.

Requirements:

• Define constants for approximate latencies: REGISTER=1, SHARED=20, L2=80, GLOBAL=600 cycles
• Simulate a kernel that reads 1024 floats per thread from each memory type
• Calculate total cycle cost for: (a) all register access, (b) all shared memory, (c) all global memory
• Calculate how many warps are needed to hide global memory latency, given that the GPU can switch warps every cycle
• Show that with enough warps (say 16), the effective throughput approaches bandwidth-bound, not latency-bound
• Print a table showing memory type, latency (cycles), bandwidth relative to global, and whether it is programmer-managed
• Include a note about register pressure: if a thread uses > 64 registers on a GPU with 64K registers per SM, occupancy drops