SIMT Execution and Divergence Simulation

SIMD: Explicit Vectors on the CPU

SIMD (Single Instruction, Multiple Data) is a processor feature where one instruction operates on a vector of data simultaneously. SSE, AVX, and NEON are SIMD instruction sets. The programmer or compiler explicitly chooses vector width and uses blend/mask instructions to handle per-lane differences.

For example, an AVX-256 add operates on eight 32-bit floats in one instruction. The programmer controls which lanes are active.

SIMT: Scalar Code, Hardware Masking

SIMT (Single Instruction, Multiple Thread) is how NVIDIA GPUs execute. One instruction broadcasts to many execution units, but you write scalar thread code. Each thread has its own registers and can branch independently. The hardware masks off inactive threads.

Consider a warp of 32 threads where thread_id % 4 == 0 takes one path and the rest take another:

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In pure SIMD, a skilled programmer might use blend instructions to handle both paths in one pass. In SIMT, divergence always serializes. AMD wavefronts of 64 threads follow the same rules.

• SIMD: programmer controls masks explicitly
• SIMT: hardware masks per branch path
• Practical rule: keep warps on uniform control flow in inner loops

For This Exercise

You will simulate SIMT execution with boolean execution masks, show two-phase divergence for an if/else, and model early-exit loops where inactive threads stay masked until all threads finish. This task requires you to print masks per phase and calculate the divergence penalty. Understanding SIMT vs SIMD explains why GPU kernels punish data-dependent branches that CPU vector code can sometimes absorb.