Demonstrate Instruction-Level Parallelism (ILP)

Independent Work in Flight

ILP is the parallelism available within a single thread when instructions do not depend on each other's results. Out-of-order cores rename registers and schedule ready ops across multiple execution units.

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The first two adds can execute in parallel; the third waits.

Limits to ILP

• True dependencies: RAW hazards limit scheduling
• Functional unit count: only so many adders and multipliers
• Memory latency: loads that miss cache stall the window

For example, unrolling a loop manually exposes more independent multiplies per iteration, raising IPC until the reorder buffer fills.

For this exercise, you will write microbenchmarks with varying dependency chains and read perf IPC. This task asks you to contrast serial chains against manually unrolled independent bodies on the same CPU.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.