Implement Simple Interrupt Handler for Timer or Keyboard

Writing IRQ handlers

Hardware interrupts arrive as IRQ lines mapped through the PIC or IOAPIC into IDT vectors. A timer ISR typically increments a tick counter and sends an EOI byte 0x20 to the master PIC at port 0x20. For example, IRQ0 remapped to vector 0x20 fires ~18.2 Hz on the legacy PIT.

Handler skeleton

nasmCopy
Loading…

• Save state: Pusha or save only clobbered registers
• EOI: Required for PIC; APIC has its own EOI register
• Shared IRQs: Chain or check device status registers
• Keep ISRs short; defer heavy work to bottom halves

APIC vs PIC

ACPI systems may route IRQs through IOAPIC entries not covered by the classic 8259 sequence. The EOI pattern you learn on the PIC still illustrates the contract: acknowledge the controller so another edge can arrive. Use a volatile tick variable if C code reads it from the main loop while the ISR writes it. Mask IRQs during table edits to avoid executing half-installed handlers.

Why for this exercise

You will install a timer or keyboard ISR that updates a counter and acknowledges the PIC. This exercise requires IDT setup, EOI discipline, and IRET without leaving interrupts masked permanently.