Measure IPC (Instructions Per Cycle) with perf

Instructions Per Cycle

IPC (retired instructions per cycle) summarizes how well the CPU utilized its front end and execution units. IPC of 1.0 on a 4-wide machine means most slots went idle; values above 2 are common on wide out-of-order cores with SIMD.

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Interpreting Results

• Low IPC + high cache misses: memory bound
• Low IPC + high branch-misses: control hazard bound
• High IPC: good parallelism or SIMD utilization

For example, a tight ADD loop on contiguous arrays might exceed 2.0 IPC while pointer-chasing serial loads sit near 0.3.

For this exercise, you will measure IPC on provided kernels and classify bottlenecks. This task asks you to connect perf counters to the pipeline concepts from earlier tasks instead of treating IPC as a magic score.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.