Design IR for JIT Compilation

IR Designed for Fast Lowering

JIT IR sits between bytecode and machine code: low enough to map quickly, high enough to optimize. JVM bytecodes, JavaScriptCore's DFG SSA, and V8's TurboFan IR are purpose-built for fast tier-up and guard insertion.

JIT IR Properties

Explicit types or tags for guard insertion. SSA for quick DCE and constant fold. Block structure mirrors control flow for patchable branches. Operands close to machine registers.

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• Lower IR in one pass for baseline JIT
• SSA names map 1:1 to stack slots or regs early
• Intrinsics for runtime calls (alloc, type check)
• IR size bounded to cap compile memory

Connecting to real compilers

Production compilers embed this step inside a longer pipeline. GCC flows through cpp, cc1, assembly, and ld; Clang uses the driver, Sema, LLVM IR passes, and a target backend. LLVM bitcode, JVM bytecode, and WASM are other familiar IRs at the same layer. The exercise isolates one pass so you can test it alone before chaining it to the next stage.

Why for this exercise

You will design IR suited for JIT compilation. This exercise asks you to define instructions that lower quickly to native code while supporting guards, type specialization, and deoptimization metadata.