Implement Register Allocation for JIT

Fast Allocation for JIT Latency

JIT compilers cannot spend seconds on graph coloring. HotSpot's C1 uses linear scan; baseline JITs may use fixed register assignments or none at all. Allocation quality matters less than compile speed for tier-one code.

Linear Scan in JIT

Sort live intervals, assign registers in one pass, spill the rest. Skip expensive coalescing. Reuse allocation across similar bytecode patterns with templates.

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• Tier-one: few registers, many memory operands
• Tier-two: better allocation after profiling
• Register pinning for calls per ABI
• Deopt maps need register-to-slot mapping

Connecting to real compilers

Production compilers embed this step inside a longer pipeline. GCC flows through cpp, cc1, assembly, and ld; Clang uses the driver, Sema, LLVM IR passes, and a target backend. LLVM bitcode, JVM bytecode, and WASM are other familiar IRs at the same layer. The exercise isolates one pass so you can test it alone before chaining it to the next stage.

Why for this exercise

You will implement register allocation tailored for JIT compilation speed. This exercise asks you to assign registers with a fast linear scan rather than full graph coloring.