Load/Store Instructions in ARM

Registers First, Memory Second

AArch64 is classic RISC: arithmetic does not target memory like x86 add [mem], eax. You ldr into a register, compute, then str back. Compilers generate clean array walks because post-increment addressing exists for exactly that job.

asmCopy
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Pre-index [x1, #8]! adjusts the base before the access; post-index [x1], #8 after.

For this exercise, you will copy and transform a small array using multiple addressing modes. This task asks you to demonstrate post-index walks, because that idiom is what makes AArch64 loop codegen shorter than equivalent x86 for array kernels.

Keep the relevant man page, ABI doc, or Rust reference chapter open while you work. When your output disagrees with the reference implementation on the same machine, the mismatch is usually an alignment rule, an off-by-one terminator, or a register slot you misread in GDB. Skim the official documentation for the tool or ABI named in the exercise; the prose changes, but register roles, syscall numbers, and ownership rules stay stable across releases.