Understand Memory Barriers and Memory Ordering

Ordering Across Cores

CPUs and compilers reorder memory operations for speed. Memory barriers (fences) restrict reordering so other cores observe writes in intended order. Lock implementations depend on acquire/release semantics.

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Architecture Fence Instructions

• x86: MFENCE, SFENCE, LFENCE; locked ops imply strong ordering
• ARM: DMB, DSB, ISB
• C11: memory_order_seq_cst maps to fences on weak ISAs

For this exercise, you will demonstrate a litmus test where missing barriers lets a second thread observe ready==1 but stale data. This task asks you to fix ordering with atomics, matching what the Linux kernel documents for spinlock release.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.