Build 1-bit Multiplexer and Demultiplexer

Multiplexer: Select One of Many

A 1-bit multiplexer (MUX) routes one of two data inputs to a single output, controlled by a select line S. When S=0, output follows I0; when S=1, output follows I1.

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MUX blocks appear everywhere: ALU operation select, register-file read ports, and memory bank switching in embedded SoCs.

Demultiplexer: Fan Out One to Many

A demultiplexer (DEMUX) is the inverse: one data input fans to one of two outputs based on S. For example, with D=1 and S=0, only O0 goes high while O1 stays 0.

• MUX: many inputs, one output (selector picks the winner)
• DEMUX: one input, many outputs (selector picks the destination)

For this exercise, you will build both circuits from AND, OR, and NOT gates. You will use the MUX in the 4-bit ALU task to choose between ADD and SUB results on the same datapath, which is exactly how real ALUs share hardware across operations.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.