Master the fundamental concepts of memory hierarchy through this focused micro-challenge.
Multi-socket servers attach local DRAM to each CPU. Accessing another socket's memory crosses an interconnect (Intel UPI, AMD Infinity Fabric) with higher latency and limited bandwidth. The OS and allocator should prefer local nodes.
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For example, allocating on node 0 then letting threads on node 1 hammer the buffer can halve bandwidth versus node-local allocation.
For this exercise, you will run the same bandwidth microbenchmark under numactl policies and compare nodes. This task asks you to quantify why PostgreSQL, Redis, and HPC jobs pin threads near their memory.
Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.
For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.
Demonstrate NUMA effects and memory allocation policies.
Requirements:
Three hints are available for this task, revealed one at a time inside the code workspace so you can struggle productively before seeing them.
All starter code and reference implementations are available for your local setup.
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