LC

Simulate Page Table Walk for Virtual-to-Physical Translation

hard8/9

Benchmark TLB (Translation Lookaside Buffer) Performance Understand NUMA: Non-Uniform Memory Access in Multi-Socket Systems

Language

Compiler

2.0s Limit 256MB

Implementation

Simulate page table walk for address translation.

Requirements:

Implement 4-level page table hierarchy (PML4, PDP, PD, PT)
Parse virtual address into fields
Walk page tables to get physical address
Handle page faults (not present)
Check permission bits
Show translation steps
Compare speed with/without TLB

Why This Matters

This 4-level PML4/PDP/PD/PT walk is the literal algorithm the MMU hardware executes on every TLB miss in real x86-64 CPUs, and it's precisely the mechanism the Meltdown vulnerability (CVE-2017-5754) abused to leak kernel memory through speculative execution. The Linux kernel's mm/ page-table code implements this exact hierarchy, and getting permission-bit checks wrong here mirrors real privilege-escalation bugs in OS memory management.

Hints

0 / 3 revealed

Validation Suite

main.c

Workspace 1.0