Program the 8259 Programmable Interrupt Controller

8259 PIC Basics

The legacy PIC cascades two chips delivering IRQ 0-15 to CPU vectors starting at 0x20. Kernel masks lines, acknowledges interrupts with EOI, and maps vectors away from CPU exceptions.

Initialization Sequence

ICW1-4 workflow:

• Remap base vector to 0x20 / 0x28
• Set cascade identity for master/slave
• Configure 8086 mode

For example, timer IRQ0 becomes vector 0x20 after remapping instead of conflicting with CPU exceptions at 0x0-0x1F.

Why This Matters in Production

Remapping the 8259 PIC's IRQ0-15 to vectors 32-47 is a mandatory step in every real x86 kernel, because without it hardware interrupts collide with CPU exception vectors 0-31 and a keyboard press could be misread as a divide-by-zero fault. Forgetting to send EOI after handling an interrupt is why a kernel's very first IRQ0 timer tick often silently hangs all future interrupts.

Debugging Checklist

Before you call the implementation done, walk failure modes on purpose. Test empty structures, single-element edge cases, maximum concurrency, and errno paths that must not crash the program. OS code usually fails in production when happy-path tests pass but invariants break under contention or memory pressure.

Implementation Notes

Keep structures small and name fields after kernel counterparts when possible. That lets you read man pages and kernel source side by side while you work. Print observable events during development; remove noisy logs once tests pass reliably.

For This Exercise

You will program PIC initialization and implement EOI in IRQ stubs. The task asks you to unmask timer IRQ only after handler registration is complete.