Transition from Protected Mode to Long Mode (x86_64)

Long mode transition

x86_64 requires protected mode with paging enabled, then activation of PAE and an LM-compatible page table before setting EFER.LME and far jumping to 64-bit code. For example, after MOV EAX, CR4; OR EAX, 0x20 enables PAE, CR3 must reference PML4 tables mapping your kernel.

Steps after protected mode

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• GDT: Needs 64-bit code descriptor (L bit set)
• Compatibility submode: First far jmp may land in compat before 64-bit CS
• Discard: Real mode and 16-bit segments after long mode entry
• Stack and IDT must use 64-bit handlers (IRETQ)

Compatibility submode

The first far jump after enabling LME may land in compatibility mode if the segment is a 32-bit code descriptor; a second far jump with a 64-bit CS clears compatibility state. Ensure PAE page tables include the high-half addresses if the kernel links above 2 GB. IRETQ is required for interrupts once running in true 64-bit mode.

Why for this exercise

You will extend paging to PAE/PML4, set EFER.LME, and jump to 64-bit code. This exercise requires PAE on before LME and a valid long-mode GDT entry for the far jump target.