Set Up the Task State Segment (TSS)

Task State Segment

The TSS holds ring-0 stack pointer and I/O map base for privilege switches on older multitasking models. Even on modern kernels, a minimal TSS is required so IST or ring transitions know which stack to use on interrupts from ring 3. For example, the x86 Linux per-CPU TSS mainly stores the ring-0 RSP for double-fault stacks.

Minimal fields

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• TR register: Points to TSS selector in GDT (busy bit managed by CPU)
• IST entries (64-bit TSS): Alternate stacks for critical exceptions
• I/O bitmap offset: Set to TSS limit to disable port traps if unused
• Hardware task switching is obsolete; software context switch replaces it

Busy bit rules

The CPU sets the TSS busy bit when loaded via LTR; do not manually edit it unless you know the double-fault implications. For minimal kernels, only ESP0 and SS0 fields matter; zero the rest. Place the TSS in memory that stays mapped after paging. The TR register holds the selector; verify it points to a system segment type 0x9 (available TSS) in the GDT.

Why for this exercise

You will define a TSS descriptor in the GDT and load it with LTR. This exercise requires a valid ESP0 and SS0 for future ring-3 entry or interrupt stack switching.