Implement Register Allocation Using Graph Coloring

Graph Coloring Allocation

IR temporaries outnumber physical registers. The classic approach builds an interference graph (nodes are temporaries, edges mean simultaneous live ranges) and colors it with K colors for K registers. Chaitin-Briggs allocation in GCC and LLVM spills uncolorable nodes to the stack.

Allocation Pipeline

Compute live ranges via dataflow. Build interference graph. Simplify and spill: nodes with degree less than K can be colored. Spill expensive nodes to memory. Emit mov loads/stores around spilled uses.

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• Coalescing merges copies to reduce moves
• Spill cost heuristic picks victim nodes
• Caller-saved vs callee-saved affects save points
• Allocation is NP-hard; heuristics suffice in practice

Connecting to real compilers

Production compilers embed this step inside a longer pipeline. GCC flows through cpp, cc1, assembly, and ld; Clang uses the driver, Sema, LLVM IR passes, and a target backend. LLVM bitcode, JVM bytecode, and WASM are other familiar IRs at the same layer. The exercise isolates one pass so you can test it alone before chaining it to the next stage.

Why for this exercise

You will implement register allocation using graph coloring on your IR. This exercise requires building the interference graph, coloring nodes, and inserting spill code when more temporaries are live than available registers.