LC

Simulate Reorder Buffer for Out-of-Order Execution

hard5/8

Measure IPC (Instructions Per Cycle) with perf Understand Memory Barriers and Memory Ordering

Language

Compiler

2.0s Limit 256MB

Implementation

Simulate reorder buffer for out-of-order execution.

Requirements:

Implement ROB data structure
Dispatch, execute, writeback, retire stages
Track instruction status
Handle in-order retirement
Demonstrate out-of-order execution
Show ROB state over time

Why This Matters

This ROB design is exactly what ships inside real chips: Intel's Golden Cove core uses a 512-entry ROB and earlier Sunny Cove used 352, precisely to keep more independent instructions in flight around slow memory operations. Precise exceptions guaranteed by in-order retirement are also why a page fault or divide-by-zero in real hardware always reports a consistent, debuggable machine state despite instructions finishing out of order.

Hints

0 / 3 revealed

Validation Suite

main.c

Workspace 1.0