Benchmark Scalar Loop Performance

Baseline Scalar Performance

Before SIMD, establish how fast a plain C loop runs. Compiler unrolling, autovectorization, and profile-guided optimization can surprise you, so measure with optimization flags documented.

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Measurement Hygiene

• Pin CPU frequency (cpufreq performance governor)
• Warm caches or report cold vs warm separately
• Repeat and take median; report variance

For example, multiplying two 1M-element float arrays might run at 200 MB/s scalar but jump an order of magnitude once vectorized.

For this exercise, you will benchmark element-wise multiply-add and record ns/element. This task asks you to save this scalar baseline because every SIMD task compares speedup against it.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.