SIMD Basics with SSE

SSE Processes Four Lanes at Once

Single Instruction Multiple Data (SIMD) is where ffmpeg, BLAS, and simdjson get their speed. SSE uses 128-bit xmm registers: four float lanes in parallel. AVX widens to 256-bit ymm; your exercise stays with SSE basics in NASM.

nasmCopy
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• movaps demands 16-byte aligned addresses; movups tolerates unaligned at a cost
• addps adds four floats pairwise, not one scalar
• Declare data with align 16 in .data

Scalar vs Vector

A scalar loop issues one add per element; SIMD issues one add for four. Auto-vectorization in Clang often fails on pointer aliasing, which is why hot paths stay hand-written.

For this exercise, you will add two four-element float arrays with SSE and store the result. This task asks you to verify alignment before movaps, because unaligned SSE on older cores faults and on modern cores still hurts throughput.

Keep the relevant man page, ABI doc, or Rust reference chapter open while you work. When your output disagrees with the reference implementation on the same machine, the mismatch is usually an alignment rule, an off-by-one terminator, or a register slot you misread in GDB. Skim the official documentation for the tool or ABI named in the exercise; the prose changes, but register roles, syscall numbers, and ownership rules stay stable across releases.