Comprehensive SIMD vs Scalar Performance Benchmark

Head-to-Head Methodology

A fair SIMD vs scalar shootout fixes clock, array size, and correctness checks. Report speedup distributions across multiple sizes (L1-fit, L2-fit, RAM) because memory hierarchy changes the winner.

cCopy
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Metrics Beyond Wall Clock

• Instructions retired (perf stat)
• Bandwidth: bytes / second = 2 * size * sizeof(T) / time for copy-like kernels
• Energy: optional RAPL counters on Intel

For example, AVX2 might show 8x speedup in L1 but only 2x in RAM when DRAM bandwidth caps both paths.

For this exercise, you will run a suite of kernels (add, dot, memset) across scalar, SSE2, and AVX2 implementations. This task asks you to plot speedup vs size and explain where SIMD stops helping, closing the vectorization subtrack with measured evidence.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.