Build SR Latch and D Flip-Flop

SR Latch: Memory from Feedback

An SR latch uses cross-coupled NOR (or NAND) gates to store one bit. Set (S) forces output high; Reset (R) forces it low. The forbidden S=1, R=1 state is why designers moved to safer clocked structures.

• S=1, R=0: latch sets to 1
• S=0, R=1: latch resets to 0
• S=0, R=0: hold previous value
• S=1, R=1: invalid (race condition)

D Flip-Flop: Edge-Triggered Storage

A D flip-flop samples input D only on a clock edge (rising or falling). Between edges the output holds stable, which is what register files and pipeline registers require.

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For example, if D=1 at the rising edge, Q becomes 1 and stays 1 until the next edge, even if D toggles wildly in between.

For this exercise, you will implement an SR latch and wrap it into a D flip-flop with enable. You will need edge-triggered behavior before building the 4-bit register that holds program state across clock cycles.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.