Implement SIMD Operations Using SSE2 Intrinsics

128-bit SIMD with SSE2

SSE2 extends x86 registers to 128 bits (__m128i, __m128d). Intrinsics map directly to instructions like PADDQ and MULPD, giving deterministic vector code without inline assembly.

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Alignment and Types

• Aligned loads: _mm_load_si128 requires 16-byte alignment
• Unaligned: _mm_loadu_si128 for heap buffers
• Horizontal sum: need shuffle/add steps to fold vector to scalar

For example, adding four 32-bit integers in one instruction uses one __m128i chunk instead of four scalar adds.

For this exercise, you will rewrite the scalar loop using SSE2 integer or double intrinsics. This task asks you to verify results bit-identical to scalar code before claiming speedup.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.