Benchmark TLB (Translation Lookaside Buffer) Performance

Translation Lookaside Buffer

Every virtual address lookup can walk page tables (four levels on x86-64). The TLB caches recent virtual-to-physical mappings. TLB misses trigger expensive page walks handled by the MMU.

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Working Set vs TLB Capacity

A 4 KiB page and a 64-entry TLB cover only 256 KiB without misses. Jumping across thousands of pages intentionally blows the TLB.

• 4 KiB pages: fine-grained mapping, more TLB pressure
• 2 MiB huge pages: fewer entries cover more RAM (common for databases)

For this exercise, you will benchmark pointer chasing across increasing page counts. This task asks you to correlate miss spikes with page-table walk cost, the same knob hugetlbfs and JVM -XX:+UseLargePages adjust in production.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.