Tomasulo's algorithm, invented for the IBM System/360 Model 91 in 1967 to speed up floating-point pipelines, is the direct ancestor of the out-of-order schedulers inside every modern Intel, AMD, and Apple Silicon core; register renaming via a RAT-like structure is still the mechanism that lets today's CPUs achieve 4-6 IPC. The reservation-station and common-data-bus design you simulate here predates but directly informed the reorder buffer covered elsewhere in this subtrack.