LC

Implement 2-Stage Pipeline and Detect Hazards

hard8/10

Add CALL and RET Support for Subroutines Add 5-Stage Pipeline: IF, ID, EX, MEM, WB

Language

Compiler

2.0s Limit 256MB

Implementation

Implement 2-stage pipeline with hazard detection.

Requirements:

Create 2-stage pipeline (FETCH, EXECUTE)
Add pipeline registers between stages
Detect data hazards (RAW dependencies)
Stall pipeline when hazard detected
Insert bubbles (NOPs) when needed
Simulate pipelined execution
Show pipeline diagram
Compare pipelined vs non-pipelined performance

Why This Matters

This toy 2-stage pipeline illustrates what every real CPU since the 1980s does to increase throughput, and the RAW data hazard you detect here is the same class of bug that once caused visible silicon quirks: early MIPS and SPARC chips required compilers to insert explicit NOPs to cover load-delay slots. Understanding hazards at this small scale is the foundation for the deeper 5-stage and out-of-order pipelines you'll build next in this subtrack.

Hints

0 / 3 revealed

Validation Suite

main.c

Workspace 1.0