LC

Add 5-Stage Pipeline: IF, ID, EX, MEM, WB

hard9/10

Implement 2-Stage Pipeline and Detect Hazards Implement Forwarding to Eliminate Unnecessary Stalls

Language

Compiler

2.0s Limit 256MB

Implementation

Implement 5-stage pipeline with hazard detection and forwarding.

Requirements:

Implement 5 pipeline stages (IF, ID, EX, MEM, WB)
Add pipeline registers between stages
Detect data hazards (RAW dependencies)
Implement forwarding to avoid stalls
Handle control hazards (branches)
Simulate pipeline execution
Show pipeline diagram
Measure speedup vs single-cycle

Why This Matters

This is the canonical MIPS-style 5-stage pipeline (IF-ID-EX-MEM-WB) from Hennessy & Patterson's Computer Architecture: A Quantitative Approach, the same structure implemented in the original MIPS R2000 and taught in nearly every university computer-architecture course. Intel's Pentium 4 famously pushed pipeline depth to 31 stages chasing clock speed, then reversed course with the shallower Core microarchitecture once hazard and power costs outweighed the frequency gains.

Hints

0 / 3 revealed

Validation Suite

main.c

Workspace 1.0