Build 4-bit ALU Supporting Multiple Operations

ALU Datapath

A 4-bit ALU performs arithmetic and logic on two nibble-wide operands. A opcode line (often fed through a MUX) selects the operation: ADD, SUB, AND, OR, XOR, or NOT.

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The carry-out from bit 3 becomes the C flag your CPU will later branch on.

Flags and Overflow

Real ALUs export status bits:

• Zero (Z): result is all zeros
• Carry (C): carry-out from MSB
• Negative (N): MSB of result is 1 (signed interpretation)
• Overflow (V): signed result out of range

For example, 7 + 1 on four signed bits overflows because 0111 + 0001 wraps to 1000 (-8 in two's complement).

For this exercise, you will combine your adder, logic gates, and MUX into one selectable ALU. This task asks you to produce both the result nibble and flag bits, because the branching and pipeline tasks downstream read those flags to decide jumps.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.