The D-flip-flop array you're wiring up here is exactly how the general-purpose register files inside x86-64 (RAX-R15), ARM64 (X0-X30), and RISC-V (x0-x31) are built, just scaled to 32 or 64 bits with read/write port multiplexing. Register access is roughly 100x faster than DRAM, which is why compiler register allocation, covered later in this platform's compilers track, is one of the highest-leverage code-generation optimizations.