Add 5-Stage Pipeline: IF, ID, EX, MEM, WB

Classic Five Stages

Modern teaching pipelines use IF (fetch), ID (decode), EX (execute), MEM (memory), and WB (writeback). Each stage advances every cycle, so five instructions can be in flight at once when the pipe is full.

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Hazards Across Five Stages

Load-use hazards are the classic pain: a LOAD in EX produces data in MEM, but the next instruction needs it in EX one cycle later. You must stall one cycle or forward from MEM/WB.

For this exercise, you will refactor your CPU into five pipeline registers. You will need stage-accurate PC and register updates to match textbook timing diagrams before adding forwarding to remove unnecessary stalls.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.