Implement a CHIP-8 Emulator: CPU, Memory, Display, Keyboard

CHIP-8 Architecture

CHIP-8 is a virtual machine from the 1970s COSMAC VIP, now the standard first emulator project. 35 opcodes, 4 KiB RAM, and a 64x32 display teach fetch-decode-execute without console hardware quirks.

Components

Core state:

• Memory: 4096 bytes, programs load at \`0x200\`
• Registers: \`V0\`..\`VF\` (8-bit), \`VF\` is carry flag for math and draw
• Stack: return addresses for \`2NNN\` calls, depth 16
• Timers: delay and sound decrement at 60 Hz
• Display: XOR sprite drawing on a monochrome framebuffer

Opcodes are 16-bit big-endian words. \`DXYN\` draws an \`N\`-byte sprite at (\`VX\`, \`VY\`).

For example, opcode \`0xA000\` sets index register \`I\` to \`0x000\`; \`0x600A\` loads 10 into \`V0\`.

\`\`\`c uint16_t opcode = (mem[pc] << 8) | mem[pc + 1]; pc += 2; \`\`\`

Design Notes

Timers must tick at roughly 60 Hz regardless of how fast you emulate CPU cycles. Games read delay timer for input debouncing; sound timer drives a buzzer flag many front ends beep on.

For This Exercise

This exercise asks you to implement the CHIP-8 CPU core with fetch-decode-execute. You will handle memory, registers, stack calls, timers, and XOR drawing for a subset of opcodes.

You will use the same mental model here when reading production interpreter source later in the track. Sketch one concrete input on paper, predict the outcome, then confirm with code. That discipline catches logic errors early and makes debugging far faster when you extend the implementation in follow-on tasks.