Understand CPU Performance Counters: Cycles, Cache Misses, Branch Mispredictions

Hardware Counters Tell You Why

Modern CPUs expose performance-monitoring units (PMUs) that count cycles, instructions retired, last-level cache misses, and branch mispredictions. Intel VTune, perf, and likwid all read the same counters. A loop can look innocent in source yet retire few instructions per cycle because cache misses dominate.

Core Events to Watch

Cycles measure wall time on CPU. cache-misses at LLC level often explain memory-bound loops. branch-misses spike when data-dependent branches defeat the predictor.

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• IPC below 1.0 on a tight loop often means stalls, not cheap math
• Counter multiplexing skews short runs; prefer runs longer than 1 second
• perf list shows events your CPU actually supports
• Correlate counters with source lines using perf annotate

Working Through the Exercise

Keep the relevant documentation open while you implement. When your output disagrees with the reference, trace one failing case by hand before changing random lines.

• Trace first: walk one failing input step by step
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

Why for this exercise

You will run perf stat on two versions of the same algorithm and compare cycles, cache misses, and branch misses. This exercise requires you to connect counter deltas to specific code changes, not just report raw numbers.