Implement Fetch-Decode-Execute Cycle for Toy ISA

The CPU Main Loop

Every processor, from a 6502 emulator to a server Xeon, repeats fetch-decode-execute. The program counter (PC) points at the next instruction byte; the decoder maps opcode bits to control signals; execute updates registers, memory, or flags.

cCopy
Loading…

Toy ISA Example

A tiny program:

cCopy
Loading…

For this exercise, you will implement this loop for the teaching ISA in the starter code. You will need correct PC advancement and operand decoding before adding the ALU, register file, and branches in later CPU design tasks.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.