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Implement Fetch-Decode-Execute Cycle for Toy ISA

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Language

Compiler

2.0s Limit 256MB

Implementation

Implement fetch-decode-execute cycle for toy ISA.

Requirements:

Define instruction format (opcode, operands)
Implement FETCH stage (read from PC, increment PC)
Implement DECODE stage (parse opcode and operands)
Implement EXECUTE stage (perform operations)
Support 4 registers (R0-R3)
Support LOAD, ADD, SUB, HALT operations
Execute programs from memory array
Print each stage of execution

Why This Matters

This fetch-decode-execute loop is literally the main loop of every CPU simulator, including QEMU's interpreter core and the 6502/Z80 emulators that power retro game emulation in MAME. Real silicon pipelines this same loop across multiple stages, but the sequential version you build here is the exact control-flow model taught in Patterson & Hennessy's Computer Organization and Design.

Hints

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Validation Suite

main.c

Workspace 1.0