Memory Coalescing: The Key to GPU Bandwidth

Write a C program that simulates memory coalescing and calculates transaction counts.

Requirements:

• Define CACHE_LINE_SIZE as 128 bytes and WARP_SIZE as 32
• Simulate three access patterns for 32 threads, each reading a 4-byte integer: (a) Coalesced: thread i reads base + i * 4 (b) Strided: thread i reads base + i * 1024 (c) Misaligned: thread i reads (base + 64) + i * 4
• For each pattern, determine how many unique 128-byte cache lines are touched
• Print the number of memory transactions required for each pattern
• Calculate bandwidth utilization: if each transaction fetches 128 bytes but only 4 are used per thread, what is the efficiency?
• Simulate a matrix row-major read (coalesced) vs column-major read (strided) for a 32x32 matrix
• Print a summary table: Pattern | Transactions | Bytes Requested | Bytes Transferred | Efficiency
• Explain why shared memory can help with uncoalesced access patterns