Build Half-Adder and Full-Adder from Gates

Half-Adder: One Bit, No Carry In

A half-adder adds two single-bit inputs and produces a sum bit plus a carry-out. It is the atomic building block inside every arithmetic unit, from a 4-bit student ALU to the 64-bit adders in modern x86 cores.

• Sum: XOR of inputs (odd number of 1s)
• Carry: AND of inputs (both must be 1)

For example, adding 1 + 1 gives sum 0 and carry 1, which is binary 10.

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Full-Adder: Chaining Carry

A full-adder adds three bits: A, B, and Cin from the previous stage. Two half-adders plus an OR gate form the standard textbook design.

• First half-adder: A + B produces intermediate sum and carry
• Second half-adder: intermediate sum + Cin
• Final carry: OR the two carry outputs

For this exercise, you will wire half-adders into a full-adder using only the gate primitives you already built. You will need carry propagation correct before the ripple-carry adder in the next task can produce 3 + 5 = 8 on four bits.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.