Simulate Digital Circuits in Hardware Simulator

Event-Driven Circuit Simulation

A hardware simulator evaluates gates and wires in topological order. When an input toggles, affected gates recompute and propagate new values downstream. Tools like Logisim, Digital, and Verilog testbenches all follow this pattern.

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Building Blocks in Software

Your simulator needs a netlist: gates as nodes, wires as edges. Each gate type (NAND, MUX, DFF) registers an evaluation function.

• Parse or construct a circuit description
• Seed inputs (clock, buttons, constants)
• Step until outputs stabilize or a clock edge fires
• Assert expected values on probe wires

For example, feeding A=1, B=0 into a half-adder should eventually show sum=1, carry=0 on the output probes after one evaluation pass.

For this exercise, you will wire every component built so far into one runnable simulator. You will need to step clocks, load registers, and trace signals through the 4-bit ALU you constructed, mirroring how verification engineers smoke-test RTL before synthesis.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.