Master the fundamental concepts of instruction set architecture through this focused micro-challenge.
A disassembler reverses assembly: bytes in, mnemonics out. A minimal x86 decoder reads one opcode byte, optionally consumes ModR/M and immediates, then prints the instruction.
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Start with a table for common one-byte opcodes:
0x90: NOP0xC3: RET0x01 /r: ADD r/m, rFor example, the byte stream 90 90 C3 disassembles to two NOPs followed by RET.
Extend ModR/M parsing to distinguish ADD EAX, EBX from ADD [RBX], EAX.
For this exercise, you will write a loop that advances ip correctly for each instruction length. This task asks you to never lose sync with the byte stream, because one wrong instruction boundary corrupts every following decode in a real debugger.
Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.
For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.
Implement mini disassembler for toy ISA.
Requirements:
Three hints are available for this task, revealed one at a time inside the code workspace so you can struggle productively before seeing them.
All starter code and reference implementations are available for your local setup.
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