Implement a NES CPU (6502): All Opcodes, Addressing Modes, Flags

The NES 6502 CPU

The Nintendo Entertainment System runs a Ricoh 2A03, a 6502 derivative at 1.79 MHz (NTSC). Emulating it means accurate fetch-decode-execute, memory maps, and cycle counting for the PPU and APU.

Address Space and Registers

6502 features:

• A, X, Y accumulators/index registers (8-bit)
• SP stack pointer on page 0x0100-0x01FF
• PC program counter
• P status with N, V, B, D, I, Z, C flags

Memory map slices:

• \`0x0000-0x07FF\` RAM (mirrored)
• \`0x8000-0xFFFF\` cartridge PRG-ROM
• PPU and APU registers via memory-mapped I/O

For example, opcode \`0xA9\` (LDA immediate) loads the next byte into A and sets Z/N flags.

Cycle accuracy matters: many PPU tricks depend on the CPU running a known number of cycles per instruction.

Design Notes

Read the memory map through a bus function so mapper chips can redirect PRG-ROM windows later. Hard-coding `0x8000` reads works for NROM only; MMC1 and UxROM need bank switching hooks.

For This Exercise

This exercise asks you to implement a 6502 CPU core with correct addressing modes for a starter opcode set. You will fetch from the NES memory map and update flags the way test ROMs expect.

You will use the same mental model here when reading production interpreter source later in the track. Sketch one concrete input on paper, predict the outcome, then confirm with code. That discipline catches logic errors early and makes debugging far faster when you extend the implementation in follow-on tasks.