Simulate Page Table Walk for Virtual-to-Physical Translation

Multi-Level Page Tables

x86-64 uses a four-level tree: PML4, PDPT, PD, PT. Each non-leaf entry points at the next table; leaf PTEs hold the physical frame plus permission bits (present, writable, user).

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Page Fault Paths

• Present bit 0: demand paging or guard page
• Writable 0 on store: copy-on-write or protection fault
• User 0 in ring 3: kernel-only mapping

For example, virtual 0x00401000 splits into indices that index each table level; a missing present bit stops the walk and raises #PF.

For this exercise, you will simulate a walk that returns a physical address or fault code. This task asks you to model PTE bits explicitly, matching what the OS track's memory manager will install when mapping heap pages.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.