Understand Privileged Instructions: What Makes an Instruction 'Supervisor Only'

User vs Supervisor Mode

Privileged instructions touch CPU state ordinary programs must not control: page tables, interrupt masks, model-specific registers, and I/O ports. Attempting them in user mode traps to the kernel.

Examples across architectures:

• x86: WRMSR, LGDT, IN/OUT (when IOPL blocks)
• ARM: MSR to system registers, WFI
• RISC-V: CSRRW, SFENCE.VMA, MRET

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Why Traps Exist

Without privilege levels, any process could remap memory, disable interrupts, or hijack devices. Operating systems rely on ring transitions (syscall, interrupt) to enter supervisor mode safely.

For this exercise, you will classify a list of mnemonics as user-safe or supervisor-only and explain what each privileged op controls. This task asks you to connect ISA privilege bits to the protection model your OS track will build on top of.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.