Add Register File: 8 General-Purpose Registers

Multi-Ported Register Storage

A register file holds the CPU's working set: eight general-purpose registers in this emulator. Real cores expose two read ports and one write port per cycle so a single instruction can fetch two operands and store a result simultaneously.

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Register R0 is often hardwired to zero in RISC ISAs; your toy CPU may treat all eight as general purpose.

Why Registers Beat Memory

Accessing a register takes one cycle and no address calculation. Reading the same data from RAM might cost 50 to 200 cycles if it misses cache. Compilers fight to keep hot variables in registers for this reason.

• Read: combinational (output appears after address setup)
• Write: synchronous (committed on clock edge)
• Bypass: forwarding paths read the register file mid-pipeline (later task)

For this exercise, you will add eight addressable registers and hook them into fetch-decode-execute. You will need two independent read ports for three-operand-style instructions before implementing stack and call instructions.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.